Saturday, July 17, 2010

TLB registers difference between R10k and MIPS64R2

Juli Mallett told me there's difference on TLB registers between R10k and MIPS64R2.
So I checked about it.

R10k TLB registers are like this:
*EntryLo register
0: G
1: V
2: D
3-5: C
6-33: PFN
34-61: Reserved
62-63: UC

*EntryHi register
0-7: ASID
8-12: Reserved
13-43: VPN2
44-61: Fill
62-63: R

And MIPS64R2 is like this:

*EntryLo register
0: G
1: V
2: D
3-5: C
6-29: PFN
30-63: Fill

*EntryHi register
0-7: ASID
8-12: Reserved
13-39: VPN2
40-61: Fill
62-63: R

It's very clear MIPS64R2 has fewer bits for PFN and VPN2, that's problem.
But, on OCTEON datasheet it looks different:
*EntryLo register when PageGrain[ELPA] = 0
0: G
1: V
2: D
3-5: C
6-29: PFN
30: XI
31: RI
32-63: Fill

*EntryLo register when PageGrain[ELPA] = 1
0: G
1: V
2: D
3-5: C
6-29: PFN
30-42: PFNX
43-61: Fill
62: XI
63: RI


*EntryHi register
0-7: ASID
8-10: Reserved
11-12: VPN2X
13-48: VPN2
49-61: Fill
62-63: R

On OCTEON, it's extended MIPS64R2 address bits. When PageGrain[ELPA] = 1, it's even larger than R10k.
And I already enabled PageGrain[ELPA], so I guess there's no problem on OCTEON to use TLB handler code for R10k.

No comments:

Post a Comment